cy24293 two outputs pci-express clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-46117 rev. *c revised april 02, 2009 features 25 mhz crystal or clock input two sets of differential pci-express clocks pin selectable output frequencies supports hcsl or lvds compatible output levels spread spectrum capability on all output clocks with pin selectable spread range 16-pin tssop package operating voltage 3.3v commercial and industrial operating temperature range functional description cy24293 is a two output pci-express clock generator device intended for networking applications. the device takes 25 mhz crystal or clock input and provides two pairs of differential outputs at 25 mhz, 100 mhz, 125 mhz, or 200 mhz for hcsl, and 25 mhz or 100 mhz for the lvds signaling standard. the device incorporates lexmark spread spectrum profile for maximum electromagnetic interf erence (emi) reduction. the spread type and amount can be selected using select pins. logic block diagram xin/exclkin clock buffer/ crystal oscillator pcie0p pcie0n pcie1n pcie1p xout ss0 ss1 s0 vddo = 475 ohms 1% gndo pll clock synthesizer r ref control logic s1 vddx gndx (25 mhz) oe ref i [+] feedback
cy24293 document number: 001-46117 rev. *c page 2 of 10 pinouts figure 1. pin diagram - cy24293 16-pin tssop tssop s0 pcie0p pcie1n s1 oe 1 8 7 6 5 4 3 2 15 14 13 12 11 10 9 16 ss0 pcie0n gndo ss1 gndx xin/exclkin pcie1p vddo xout iref vddx table 1. pin definitions - cy24293 16-pin tssop pin number pin name pin type description 1 s0 input frequency select pin. has internal weak pull up. refer to table 2 . 2 s1 input frequency select pin. has internal weak pull up. refer to table 2 . 3 ss0 input spread spectrum select pin 0. has internal weak pull up. refer to ta b l e 3 . 4 xin/exclkin input crystal or clock input. 25 mhz fundamental mode crystal or clock input. 5 xout output crystal output. 25 mhz fundamenta l mode crystal input. float for clock input. 6 oe input high true output enable pin. when set low, pci-e outputs are tri-stated. has internal weak pull up. 7 gndx power ground 8 ss1 input spread spectrum select pin 1. has internal weak pull up. refer to ta b l e 3 . 9 iref output current set for all differ ential clock drivers. connect 475 resistor to ground. 10 pcie1n output differential pci-express complementary clock output. tristated when disabled. 11 pcie1p output differential pci-express true clock output. tristated when disabled. 12 vddo input 3.3v power supply for output driver and analog circuits. 13 gndo power ground 14 pcie0n output differential pci-express complementary clock output. tristated when disabled. 15 pcie0p output differential pci-express true clock output. tristated when disabled. 16 vddx input 3.3v power supply for oscillator and digital circuits. table 2. output selection table s1 s0 pcie0[n,p], pcie1[n,p] 00 25 mhz 0 1 100 mhz 1 0 125 mhz 1 1 200 mhz table 3. spread selection table ss1 ss0 spread% 00 no spread 01 -0.5% 10 -0.75% 11 no spread [+] feedback
cy24293 document number: 001-46117 rev. *c page 3 of 10 application information crystal recommendations cy24293 requires a parallel resonance crystal. substituting a series resonance crystal ca uses the cy24293 to operate at the wrong frequency and violate the ppm specification. for most applications, there is a 300 ppm frequency shift between series and paral lel crystals due to incorrect loading. crystal loading crystal loading plays a critical role in achieving low ppm performance. to realize low ppm performance, consider the total capacitance the crystal sees to calculate the appropriate capacitive loading (cl). figure 2 shows a typical crystal configuration using two trim capacitors. it is important to note that the trim capacitors in series with the crystal are not parallel. it is a common misconception that load capacitors are in para llel with the crystal and must be approximately equal to the load capacitance of the crystal. this is not true. calculating load capacitors in addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. as mentioned in the previous section, the capacitance on each side of the crystal is in series with the crystal. this means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1, ce2) must be calculated to provide equal capacitive loading on both sides. figure 2. crystal loading example use the following formulas to calc ulate the trim capacitor values for ce1 and ce2: cl ................................................... crystal load capacitance cle........... .............. ................ actual loading seen by crystal using standard value trim capacitors ce ..................................................... external trim capacitors cs ......................................... .....stray capaci tance (terraced) ci ......................................... ................. internal capacitance current source (iref) reference resistor if the board target trace impedance (z) is 50 , then for r ref = 475 (1% ) , provides iref of 2.32 ma. the output current (i oh ) is equal to 6*iref. output termination the pci-express differential clock outputs of the cy24293 are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are explained in the section pci-express layout guidelines on page 4. the cy24293 can also be configured for lvds compatible voltage levels. refer to the section lvds compatible layout guidelines on page 5. table 4. crystal recommendations frequency cut load cap eff series rest (max) drive (max) tolerance (max) stability (max) aging (max) 25.00 mhz parallel 16 pf 30 1.0 mw 30 ppm 10 ppm 5 ppm/yr. xtal ce2 ce1 cs1 cs2 x1 x2 ci1 ci2 clock chip trace 2.8 pf trim 26 pf pin 3 to 6p load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 ( ) 1 = cle [+] feedback
cy24293 document number: 001-46117 rev. *c page 4 of 10 pcb layout recommendations for optimum device performance and the lowest phase noise, the following guidelines must be observed: 1. each 0.01 f decoupling capacitor must be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias must be used between the decoupling capacitor and the vdd pin. 3. the pcb trace to the vdd pin and the ground via must be kept as short as possible. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other si gnal traces must be routed away from the cy24293. this in cludes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. decoupling capacitors the decoupling capacitors of 0.01 f must be connected between vdd and gnd as close to the device as possible. do not share ground vias between components. route power from the power source through the capacitor pad and then into the cy24293 pin. pci-express layout guidelines hcsl compatible layout guidelines figure 3. pci-express device routing table 5. common recommendati ons for differential routing differential routing [1] dimension or value unit l1 length, route as non-coupled 50 trace 0.5 max inch l2 length, route as non-coupled 50 trace 0.2 max inch l3 length, route as non-coupled 50 trace 0.2 max inch r s 33 r t 49.9 table 6. differential routing for pci-express load or connector differential routing [1] dimension or value unit l4 length, route as coupled microstrip 100 differential trace 2 to 32 inch l4 length, route as coupled stripline 100 differential trace 1.8 to 30 inch note 1. refer to figure 3 . l4 l1 l2 l4 l1 l2 l3 l3 output buffer pci express load or connector rs r t r t r s [+] feedback
cy24293 document number: 001-46117 rev. *c page 5 of 10 lvds compatible layout guidelines figure 4. lvds device routing table 7. common recommendati ons for differential routing differential routing [2] dimension or value unit l1 length, route as noncoupled 50 trace 0.5 max inch l2 length, route as noncoupled 50 trace 0.2 max inch l3 length, route as noncoupled 50 trace 0.2 max inch r p 100 r q 150 r s 33 r t 49.9 table 8. lvds device differential routing differential routing [2] dimension or value unit l4 length, route as co upled microstrip 100 differential trace 2 to 32 inch l4 length, route as coupled stripline 100 differential trace 1.8 to 30 inch note 2. refer to figure 4 . l4 l1 l2 l4 l1 l2 l3 l3 output buffer lvds device input rs rs r t r t r p r q [+] feedback
cy24293 document number: 001-46117 rev. *c page 6 of 10 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. table 9. absolute maximum ratings parameter description condition min max unit v dd supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd +0.5 v t s temperature, storage non functional ?65 +150 c t j temperature, junction non functional ?65 +150 c esd hbm esd protection (human body model) jedec eia/jesd22-a114-e 2000 ? v ul-94 flammability rating v-0 at 1/8 in. msl moisture sensitivity level 3 recommended oper ation conditions parameter description min typ max unit v dd supply voltage 3.0 ? 3.6 v t ac commercial ambient temperature 0 ? +70 c t ai industrial ambient temperature ?40 ? +85 c t pu power up time for all v dd to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms note 3. parameters are guaranteed by design and char acterization. not 100% tested in production dc electrical characteristics unless otherwise stated, vdd = 3.3v 0.3v, ambient temperature = -40 c to +85 c industrial, 0c to +70c commercial parameter [3] description condition min typ max unit v il input low voltage -0.3 ? 0.8 v v ih input high voltage 2.0 ? v dd +0.3 v v ol output low voltage of pcie0[p/n], pcie1[p/n] hcsl termination (r s = 33 , r t = 49.9 ) -0.2 0 0.05 v v oh output high voltage of pcie0[p/n], pcie1[p/n] hcsl termination (r s = 33 , r t = 49.9 ) 0.65 0.71 0.85 v i dd operating supply current no load, oe = 1 ? 45 60 ma i ddod output disabled current oe = 0 ? ? 50 ma c in input capacitance all input pins ? 5 ? pf r pu pull up resistance s0, s1, ss0, ss1, oe ? 70k ? [+] feedback
cy24293 document number: 001-46117 rev. *c page 7 of 10 , test and measurement setup ac electrical characteristics unless otherwise stated: vdd = 3.3v 0.3v, ambient temperature = -40 c to +85 c industrial, 0c to +70c commercial, outputs hcsl terminated. parameter [3] description condition min typ max unit f in input clock frequency (crystal or external clock) ?25?mhz f out output frequency hcsl termination ? ? 200 mhz lvds termination ? ? 100 mhz f err frequency synthesis error ? 0 ? ppm t ccj cycle-to-cycle jitter [4] ??75ps sp mod spread modulation frequency ? 32 ? khz t dc output clock duty cycle [4,6] 45 50 55 % t oeh output enable time oe going high to differential outputs becoming valid ? ? 200 ns t oel output disable time oe going low to differential outputs becoming invalid ? ? 200 ns t lock clock stabilization from power up measured from 90% of the applied power supply level ?12ms t r output rise time [4,5] measured from 0.175v to 0.525v 130 ? 700 ps t f output fall time [4,5] measured from 0.525v to 0.175v 130 ? 700 ps dt r rise time variation [4,5] for a given frequency, max(t r ) - min (t r ) ? ? 125 ps dt f fall time variation [4,5] for a given frequency, max(t f ) - min (t f ) ? ? 125 ps t oskew output skew [6] measured at v cross point ? ? 50 ps v cross absolute crossing point voltage [6,7] 0.25 0.35 0.55 v v xdelta variation of v cross over all clock edges [6,8] ? ? 140 mv notes 4. measured with cload = 4 pf max. (scope probe + trace load) 5. measurement taken from a differential waveform. 6. measured at crossing point where the instantaneous voltage value of the rising edge of pciep equals the falling edge of pcien . 7. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. 8. refers to the difference between the pciep rising edge v cross average value and the pcien rising edge v cross average value. figure 5. test load configuration for differential output signals cload pciep pcien 475 ohm 33 ohm 50 ohm cload 33 ohm 50 ohm [+] feedback
cy24293 document number: 001-46117 rev. *c page 8 of 10 package dimensions figure 6. 16-pin tssop 4.40 mm body package ordering information part number type production flow pb-free CY24293ZXC 16-pin tssop commercial, 0c to 70c CY24293ZXCt 16-pin tssop tape & reel commercial, 0c to 70c cy24293zxi 16-pin tssop industrial, -40c to 85c cy24293zxit 16-pin tssop tape & reel industrial, -40c to 85c 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin 1 id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05gms part # z16.173 standard pkg. zz16.173 lead free pkg. [+] feedback
cy24293 document number: 001-46117 rev. *c page 9 of 10 document history page document title: cy24293 two outputs pci-express clock generator document number: 001-46117 rev. ecn no. orig. of change submission date description of change ** 2490167 pyg/dpf/aesa see ecn new data sheet *a 2507681 dpf/aesa 05/23/2008 added note 1: parameters are guaranteed by design and characterization. not 100% tested in production. added note 2 for duty cycle spec in the ac elect. characteristics. added hcsl termination in condition for v ol , v oh dc elect. char. added v xdelta value of 140 mv in the differential 100 mhz hcsl output. changed cload from 2 pf to 4 pf in note 2. added internal weak pull ups for s0, s1, ss0, ss1 and oe pins. updated t oeh and t oel to 200 ns (max.). updated data sheet template *b 2621901 cxq/aesa 12/19/2008 updated i dd spec in dc electrical characteristics. added max spec for i ddod dc electrical characteristics. added r pu in dc electrical characteristics. replaced t rfvar with dt r and dt f in ac electrical characteristics. added definitions for rise and fall time variation, crossing point variation in ac electrical characteristics. reduced cycle-to-cycle jitter spec to 75ps in ac electrical characteristics. *c 2683343 cxq/pyrs 04/03/2009 removed ?prelimin ary? from datasheet title and headings added ?max? to crystal esr spec. changed ?lvds down device? to ?lvds device? in table 8 and figure 4. [+] feedback
document number: 001-46117 rev. *c revised april 02, 2009 page 10 of 10 all products and company names mentioned in this document may be the trademarks of their respective holders. cy24293 ? cypress semiconductor corporation, 2008-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb [+] feedback
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